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1 for more information www.linear.com/ltm4651 typical application features description en55022b compliant 58v, 24w inverting-output dc/dc module regulator the lt m ? 4651 is an ultralow noise, 58v, 24w dc/dc module ? inverting topology regulator. it regulates a nega - tive output voltage (v out C ) from a positive input supply voltage (v in ), and is designed to meet the radiated emissions requirements of en55022. conducted emission require - ments can be met by adding standard filter components. included in the package are the switching controller , power mosfets, inductor, filters and support components. the ltm4651 can regulate v out C to a value between C 0.5v and C 26.5v , provided that its input and output voltages adhere to the safe operating area criteria of the ltm4651: v in? +? |v out C | 58v . a switching frequency range of 250khz to 3mhz is supported (400khz default) and the module can synchronize to an external clock. despite being an inverting topology regulator, no level shift circuitry is needed to interface to the ltm4651 s run, pgood or clkin pins; those pins are referenced to gnd. the ltm4651 is offered in a 15mm 9mm 5.01mm bga package with snpb or rohs compliant terminal finish. C24v, 2.25a* ultralow noise** dc/dc module regulator applications n complete low emi switch mode power supply n en55022 class b compliant n wide input voltage range: 3.6v to 58v n up to 4a output current n 24w output from 12v in to C24v out , p loss = 5w, t a = 60c, t rise = 60c, 200lfm n output voltage range: C26.5v v out C C0.5v n safe operating area: v in + |v out C | 58v n 1.67% total dc output voltage error over line, load and temperature (C40c to 125c) n parallel and current share with multiple ltm4651s n constant-frequency current mode control n frequency synchronization range: 250khz to 3mhz n power good indicator and programmable soft-start n overcurrent/overvoltage/overtemperature protection n 15mm 9mm 5.01mm bga package n avionics, industrial control and test equipment n video, imaging and instrumentation n 48v telecom and network power supplies n rf systems l , lt, ltc, ltm, linear technology , the linear logo, ltpowercad and module are registered trademarks of analog devices, inc. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5705919, 5847554, 6580258. output current capability* pins not used in this circuit: clkin, pgood, pgdfb, sw, extv cc temp + , temp ? , nc iseta gnd isetb v in sv in v d run intv cc vinreg compa compb f set pgnd gnd sns sv out ? v out ? ltm4651 ?24v out , up to 2.25a 10f 2 load 90.9k 481k 4.7 f 4.7 f v in 3.6v to 34v 4651 ta01a **see figures 5 ? 8 for dc2328a radiated emission performance against en55022b limits. *current limit frequency-foldback activates at load currents higher than indicated curves. continuous output current capability subject to details of application implementation. switching frequency set per table 1. see notes 2 and 3. v out ? = ?0.5v v out ? = ?3.3v v out ? = ?5v v out ? = ?8v v out ? = ?12v v out ? = ?15v v out ? = ?20v v out ? = ?24v lt m4651 4651f 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 output current (a) input voltage (v) 4651 ta01b 0 10 20 30 40 50 60
2 for more information www.linear.com/ltm4651 pin configuration absolute maximum ratings terminal voltages v in , v d , sv in , sw, pgnd, gnd sns , iseta .. C 0.3v to 60v gn d, extv cc ........................................ C 0.3 v to 28v ru n ................................. gn d C 0.3v to v out C + 60v in tv cc , pgdfb, vinreg, compa .......... C 0.3 v to 4v f set .................................................. C 0.3 v to intv cc compb ................................................... C 0. 3 v to 5v i setb .................................................... C 0. 3v to 28v cl kin, pgood (relative to gnd) ........... C 0. 3v to 6v terminal currents in tv cc peak output current (note 8) ................ 30m a t emp + .................................................. C 1ma to 10ma t emp C ................................................. C 10m a to 1ma temperatures in ternal operating temperature range (notes 2, 7).......................... C 40 c to 125 c st orage temperature range .............. C 55 c to 125 c pe ak solder reflow package body temperature ............................................ 245 c (note 1) (all voltages relative to v out C unless otherwise indicated) 1 a b c d e f g h j k l 2 3 4 top view bga package 77-pin (15mm 9mm 5.01mm) 5 6 7 v in v d pgnd temp ? nc nc v out ? nc sw gnd sv in vinreg sv out ? f set run pgood pgdfb clkin v out ? v out ? sv out ? gnd sns extv cc intv cc compb compa isetb iseta temp + temp ? temp + nc t jmax = 125c jctop = 22.4c/w, jcbottom = 7.9c/w, jb = 9.6c/w, ja = 20.8c/w values determined per jesd51-12 weight = 1.8 grams order information part number pad or ball finish part marking* package type msl rating temperature range (see note 2) device finish code ltm4651ey#pbf sac305 (rohs) ltm4651y e1 bga 3 C40c to 125c ltm4651iy#pbf C40c to 125c ltm4651iy snpb (63/37) e0 C40c to 125c ? device temperature grade is indicated by a label on the shipping container. ? pad or ball finish code is per ipc/jedec j-std-609. ? terminal finish part marking: www.linear.com/leadfree ? this product is not recommended for second side reflow. for more information, go to www.linear.com/bga-assy ? recommended bga pcb assembly and manufacturing procedures: www .linear.com/bga-assy ? bga package and tray drawings: www.linear.com/packaging ? this product is moisture sensitive. for more information, go to: www .linear.com/bga-assy http://www.linear.com/product/ltm4651#orderinfo lt m4651 4651f
3 for more information www.linear.com/ltm4651 the l denotes the specifications which apply over the specified internal operating temperature range (note 2). t a = 25 c , test circuit 1, v in = 24v and electrically connected to sv in and run, iseta C sv out C = 24v , extv cc = pgnd, clkin open circuit, r fset = 57.6k and r iset = 480k and voltages referred to pgnd unless otherwise noted. symbol parameter conditions min typ max units sv in(dc) , v in(dc) input dc voltage v in + |v out C | 58v l 3.6 58 v v out(range) C range of output voltage regulation 0.5v iseta C sv out C 26.5v l C 26.5 C0.5 v v out(C24vdc) C output voltage total variation with line and load at v out C = C24v 3.6v v in 34v, 0a i out C 0.3a, clkin driven per note 6, c inh = 4.7f, c d = 4.7f 2, c outh = 47f 2 l C 24.4 C24 C 23.6 v v out(C5vdc) C output voltage total variation with line and load at v out C = C5v measuring gnd sns ?C?iseta 12v v in 53v, 0a i out C 3a, clkin driven by 550khz clock, c inh = 4.7f, c d = 4.7f 2, c outh =?47f 2, iseta C sv out C = 5v l C15 0 15 mv v out(C0.5vdc) C output voltage total variation with line and load at v out C = C0.5v measuring gnd sns ?C?iseta 3.6v v in 28v, 0a i out C 2a, c inh = 4.7f, c d ?= 4.7f 2, c outh = 47f 2, r fset = n/u, iseta?C?sv out C = 500mv, clkin driven by 200khz clock (note 5) l C15 0 15 mv input specifications v in(uvlo) sv in undervoltage lockout threshold sv in rising sv in falling hysteresis l l l 2.1 400 3.2 2.5 700 3.6 2.8 v v mv v in(ovlo) sv in overvoltage lockout rising (note 4) 64 68 v v in(hys) sv in overvoltage lockout hysteresis (note 4) 2 4 v i inrush(vin) input inrush current at start-up c inh = 4.7f, c d = 4.7f 2, c outh = 47f 2; i out C = 0a, iseta electrically connected to isetb 1.1 a i q(svin) input supply bias current shutdown, run = gnd run = v in 16 450 30 a a i s(vin) input supply power converter clkin open circuit, i out C = 2a 2.3 a i s(vin, shutdown) input supply current in shutdown shutdown, run = gnd 4 a output specifications i out C v out C output continuous current?range from v in = 24v, regulating v out C = C 24v at f sw = 1.5mhz from v in = 12v, regulating v out C = C 5v at f sw = 550khz (see note 3, capable of up to 4a output current for some combinations of v in , v out C , and f sw ) 0 0 2 3 a a ?v out(line) C /v out C line regulation accuracy i out C = 0a, 3.6v v in 34v, iseta?C?sv out C = 24v, clkin driven by 1.8mhz clock l 0.05 0.25 % ?v out(load) C /v out C load regulation accuracy v in = 24v, 0a i out C 2a, clkin driven by 1.5mhz clock, r fset = 57.6k, and r iset = 480k l 0.05 0.5 % v out(ac) C output voltage ripple, v out C v in = 12v, iseta?C?sv out C = 5v 10 mv pCp f s v out ripple frequency v in = 12v, iseta?C?sv out C = 5v l 1.7 1.95 2.2 mhz ?v out(start) C turn-on overshoot 8 mv t start turn-on start-up time delay measured from v in toggling from 0v to 24v to pgood exceeding 3v above gnd; pgood having a 100k? pull-up to 3.3v with respect to gnd, vpgfb resistor-divider network as shown in test circuit 1, r iseta = 480k, iseta electrically connected to isetb, and clkin driven with 1.2mhz clock l 4 9 ms ?v out(ls) C peak output voltage deviation for dynamic load step i out C : 0a to 1a and 1a to 0a load steps in 1s, c outh ?= 47f 2 x5r 400 mv t settle settling time for dynamic load step i out C : 0a to 0.5a and 0.5a to 0a load steps in 1s, c outh = 47f 2 x5r 50 s electrical characteristics lt m4651 4651f
4 for more information www.linear.com/ltm4651 the l denotes the specifications which apply over the specified internal operating temperature range (note 2). t a = 25 c , test circuit 1, v in = 24v and electrically connected to sv in and run, iseta C sv out C = 24v , extv cc = pgnd, clkin open circuit, r fset = 57.6k and r iset = 480k and voltages referred to pgnd unless otherwise noted. symbol parameter conditions min typ max units i out(ocl) C i out C output current limit 2.45 a control section i iseta reference current of iseta pin v iseta? C?sv out C = 0.5v, 3.6v v in 28v 0.1v v iseta? C?sv out C v in? C?sv out C 58v l l 49.3 49 50 50 50.7 51 a a i gndsns gnd sns leakage current v in? C?sv out C = sv in? C?sv out C = run?C?gnd = iseta C?sv out C = 58v 600 a t on(min) minimum on-time (note 4 ) 60 ns v run run turn-on/-off thresholds run input turn-on threshold, run rising run hysteresis (run thresholds measured with respect to gnd) l 1.08 1.2 130 1.32 v mv i run run leakage current v in? C?48v, run?C?gnd = 3.3v l 0.1 50 na oscillator and phase-locked loop (pll) f osc oscillator frequency accuracy v in = 12v, iseta?C?sv out C = 5v, and: f set open circuit r fset = 57.6k (see f s specification) l 360 400 1.95 440 khz mhz f sync pll synchronization capture range v in = 12v, iseta?C?sv out C = 5v, clkin driven with a gnd-referred clock toggling from 0.4v to 1.2v and having a clock duty cycle: from 10% to 90%; f set open circuit from 40% to 60%; r fset = 57.6k 250 1.3 550 3 khz mhz v clkin clkin input threshold v clkin rising, with respect to gnd v clkin falling, with respect to gnd 1.2 0.4 v v i clkin clkin input current v clkin = 5v with respect to gnd v clkin = 0v with respect to gnd C20 230 C5 500 a a power good feedback input and power good output ov pgdfb output overvoltage pgood upper threshold pgdfb rising, differential voltage from pgdfb to?sv out C l 620 645 675 mv uv pgdfb output undervoltage pgood lower threshold pgdfb falling, differential voltage from pgdfb to?sv out C l 525 555 580 mv ?v pgdfb pgood hysteresis pgdfb returning 8 mv r pgdfb resistor between pgdfb and sv out C 4.94 4.99 5.04 k r pgood pgood pull-down resistance v pgood = 0.1v with respect to gnd, v pgdfb C sv out C < uv pgdfb or v pgdfb? C ? sv out C > ov pgdfb 700 1500 i pgood(leak) pgood leakage current v pgood = 3.3v with respect to gnd, uv pgdfb < v pgdfb? C?sv out C < ov pgdfb 0.1 1 a t pgood(delay) pgood delay pgood low to high (note 4) pgood high to low (note 4) 16/f sw(hz) 64/f sw(hz) s s electrical characteristics lt m4651 4651f
5 for more information www.linear.com/ltm4651 the l denotes the specifications which apply over the specified internal operating temperature range (note 2). t a = 25 c , test circuit 1, v in = 24v and electrically connected to sv in and run, iseta C sv out C = 24v , extv cc = pgnd, clkin open circuit, r fset = 57.6k and r iset = 480k and voltages referred to pgnd unless otherwise noted. note 1: stresses beyond those listing under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating conditions for extended periods may affect device reliability and lifetime. note 2: the ltm4651 is tested under pulsed load conditions such that t j ??t a . the ltm4651e is guaranteed to meet performance specifications over the 0c to 125c internal operating temperature range. specifications over the full C40c to 125c internal operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4651i is guaranteed to meet specifications over the full internal operating temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: see output current derating curves for different v in , v out , and t a , located in the applications information section. note 4: minimum on-time, v in overvoltage lockout and overvoltage lockout hysteresis, pgood delay, and extv cc switchover threshold are tested at wafer sort. note 5: v out(C0.5vdc) C low line regulation is tested at 3.6v in , with f set and clkin open circuit. high line regulation is tested at 28v in , and with clkin driven at 200khzso as to ensure minimum on time criteria is met. the ltm4651 is not recommended for applications where the minimum on- time criteria (guardband to 90ns) is continuously violated. the ltm4651 can ride through events (such as v in surge) where the on-time criteria is transiently violated. see the applications information section. note 6: v out(C24vdc) C is tested at 3.6v in and 34v in , with clkin driven with a 1.8mhz clock, iseta C sv out C = 24v, and r fset = 57.6k. it is also tested at 24v in , with clkin driven with a 1.5mhz clock, r fset = 57.6k, and r iset = 480k. note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 8: the intv cc abs max peak output current is specified as the sum of current drawn by circuits internal to the module biased off of intv cc and current drawn by external circuits biased off of intv cc . see the applications information section. symbol parameter conditions min typ max units input voltage regulation pin v vinreg vinreg servo voltage vinreg voltage during output current regulation, measured with respect to sv out C l 1.8 2.0 2.2 v i vinreg vinreg leakage current vinreg?C?sv out C = 2v 1 na intv cc regulator v intvcc channel internal v cc voltage, no intv cc loading (i intvcc = 0ma) 3.6v sv in? C?sv out C 58v, extv cc = open circuit 5v sv in? C ?sv out C 58v, 3.2v extv cc? C ?v out C 26.5v (intv cc measured with respect to v out C ) 3.15 2.85 3.4 3.0 3.65 3.15 v v v v extvcc(th) extv cc switchover voltage (note 4) 3.15 v ?v intvcc(load) / v intvcc intv cc load regulation 0ma i intvcc 30ma C2 0.5 2 % temperature sensor ?v temp temperature sensor forward voltage, v temp + C v temp C i temp + = 100a and i temp C = C100a at t a = 25c 0.6 v tc ?v(temp) ?v temp temperature coefficient C2.0 mv/ c electrical characteristics lt m4651 4651f
6 for more information www.linear.com/ltm4651 typical performance characteristics C12v efficiency vs load current C15v efficiency vs load current C24v efficiency vs load current rated operating output voltage C3.3v efficiency vs load current C5v efficiency vs load current t a = 25c, unless otherwise noted. lt m4651 4651f 2 3 4 70 75 80 85 90 95 efficiency (%) 5v in , 400khz 4651 g01 load current (a) 0 1 2 3 4 70 75 80 12v in , 400khz 85 90 95 efficiency (%) 4651 g02 5v in , 400khz 12v in , 550khz 24v in , 600khz 36v in , 600khz 48v in , 600khz 24v in , 450khz load current (a) 0 0.5 1 1.5 2 2.5 3 3.5 70 36v in , 500khz 75 80 85 90 95 efficiency (%) 4651g03 5v in , 475khz 12v in , 825khz 24v in , 1.1mhz 48v in , 500khz 36v in , 1.2mhz load current (a) 0 0.5 1 1.5 2 2.5 3 70 load current (a) 75 80 85 90 95 efficiency (%) 4651 g04 5v in , 500khz 12v in , 875khz 24v in , 1.2mhz 0 36v in , 1.4mhz 5v in , 550khz 12v in , 1mhz 24v in , 1.5mhz load current (a) 0 0.5 1 1.5 2 1 70 75 80 85 90 95 efficiency (%) 4651 g05 safe operating area input voltage (v) 0 ?20 ?15 ?10 ?5 0 output voltage (v) 4651 g06 10 20 30 40 50 60 ?30 ?25
7 for more information www.linear.com/ltm4651 typical performance characteristics start-up, pre-bias short circuit, no load short circuit, 1.25a load C24v transient response, 12v in start-up, no load start-up, 1.25a load C5v transient response, 24v in t a = 25c, unless otherwise noted. figure 32 circuit, 24v in , c inout = c in = c dgnd = c d = 4.7f, c out = 47f 2, r fset = 665k, r iset = 100k, r pgdfb = 36.5k, r extvcc = 20, 1.8a to 3.8a load step at 2a/s 40s/div v out ? 100mv/div ac-coupled i out 1a/div figure 32 circuit, 0.625a to 1.25a load step at 0.625a/s 20s/div v out ? 100mv/div ac-coupled i out 0.4a/div figure 32 circuit, application of 12v in , start-up into no load 1ms/div v in 5v/div run 2v/div pgood 5v/div v out ? 10v/div figure 32 circuit, application of 12v in , start-up into 19.2 load 1ms/div v in 5v/div i out 500ma/div pgood 5v/div v out ? 10v/div figure 32 circuit, v out ? pre-biased to ?5v through a 1n4148 diode prior to run toggling high 1ms/div v out ? 10v/div run 2v/div pgood 2v/div i diode 100ma/div figure 32 circuit, no load prior to application of v out ? short-circuit 10s/div v out ? 10v/div i in 10a/div figure 32 circuit, 19.2 load prior to application of v out ? short-circuit 10s/div v out ? 10v/div i in 10a/div lt m4651 4651f 4651 g07 4651 g08 4651 g09 4651 g10 4651 g11 4651 g12 4651 g13
8 for more information www.linear.com/ltm4651 pin functions v in ( a1 C a3, b3): power input pins. apply input voltage and input decoupling capacitance directly between v in and a power ground (pgnd) plane. v d ( a4, b4, c4 ): drain of the converter s primary switching mosfet. apply at least one 4.7f high frequency ceramic decoupling capacitor directly from v d to v out C . give this capacitor higher layout priority (closer proximity to the module) than any v in decoupling capacitors. sv in (c3): input voltage supply for small-signal circuits. sv in is the input to the intv cc ldo. connect sv in directly to v in . no decoupling capacitor is needed on this pin. v out C ( a5, b5, c2, c5, d5, e5, f5, g4 C 5, h3, h5, j3 ?C 5, k4 C 5, l4 C 5): negative power output of the ltm4651. connect all v out C pins to the application s v out C plane. apply the output filter capacitor and the output load between these and the pgnd pins. pgnd (k1 C 3, l1 C 3): power ground pins of the ltm4651. electrically connect all pins to the application s pgnd plane. gnd (d4 ): ground reference for run, clkin, and pgood signals. connect gnd directly to the pgnd power ground plane. gnd sns ( g1, h1): voltage sense, pgnd input and feed - back signal. connect gnd sns to pgnd at the point of load (pol). pins g1 and h1 are electronically connected to each other internal to the module, and thus it is only necessary to connect one gnd sns pin to pgnd at the pol. the remaining gnd sns pin can be used for redundant con - nectivity or routed to an ict test point for design-for-test considerations, as desired. sv out C ( e4, g2, h2 ): voltage sense, v out C input. connect pin h2 to v out C directly under the ltm4651. the sv out C pins at locations e4 and g2 are electrically connected to each other internal to the module, and thus it is only necessary to connect one sv out C pin to v out C under the module. the remaining sv out C pins can be used for redundant connectivity or routed to an ict test point for design-for-test considerations, as desired. run (f4): run control pin. a voltage above 1.2v (with respect to gnd) commands the module to regulate its output voltage. undervoltage lockout (uvlo) can be implemented by connecting run to the midpoint node formed by a resistor-divider between v in and gnd. run features 130mv of hysteresis. see the applications in - formation section. int v cc (g3): internal regulator, 3.3v output with re - spect to v out C . internal control circuits and mosfet- drivers derive power from intv cc bias. when operating 3.6v? 1.2v ). no external decoupling is required. when run is logic low (run? C?gnd? 4v , realize this benefit by connecting extv cc to pgnd through a resistor. (see the application information section for resistor value.) when taking advantage of this extv cc feature, locally decouple extv cc to v out C with a 1f ceramic capacitor otherwise, leave extv cc open circuit. isetb (f1): 1.5nf soft-start capacitor. connect isetb to iseta to achieve default soft-start characteristics, if desired otherwise, leave isetb open circuit. see iseta. iseta ( f2): accurate 50a current source. positive input to the error amplifier. connect a resistor (r set ) from this pin to sv out C to program the desired ltm4651 output volt - age, v out C = Cr set ? 50a . a capacitor can be connected from iseta to sv out C to soft-start the output voltage and reduce start-up inrush current. connect iseta to isetb in order to achieve default soft-start, if desired. see isetb. package row and column labeling may vary among module products. review each package layout carefully. lt m4651 4651f
9 for more information www.linear.com/ltm4651 in addition, the output of the ltm4651 can track a voltage applied between the iseta pin and the sv out C pins. see the applications information section. pgood (d1): power good indicator, open-drain output pin. pgood is high impedance when pgdfb C sv out C is within approximately 7.5% of 0.6v. pgood is pulled to gnd when pgdfb C sv out C is outside this range. pgdfb (d2): power good feedback programming pin. connect pgdfb to gnd sns through a resistor, r pgdfb . r pgdfb configures the voltage threshold of v out C for which pgood toggles its state. if the pgood feature is used, set r pgdfb to: r pgdfb = | v out C | 0.6v C 1 ? ? ? ? ? ? ? ? ? ? ? 4.99k otherwise, leave pgdfb open circuit. a small filter capacitor (220pf) internal to the ltm4651 on this pin provides high frequency noise immunity for the pgood output indicator. f set (e3): oscillator frequency programming pin. the default switching frequency of the ltm4651 is 400khz. often, it is necessary to increase the programmed fre - quency by connecting a resistor between f set and sv out C . (see the applications information section.) note that the synchronization range of clkin is approximately 40% of the oscillator frequency programmed by the f set pin. clkin (b1 ): oscillator synchronization input. leave clkin open circuit for forced continuous mode operation. alternatively, this pin can be driven so as to synchronize the switching frequency of the ltm4651 to a clock signal. in this condition, the ltm4651 operates in forced-continuous mode and the cycle-by-cycle turn-on of the primary mos - fet is coincident with the rising edge of the clock applied to clkin. note the synchronization range of clkin is ap - proximately 40% of the oscillator frequency programmed by the f set pin. see the applications information section. compa (e2): current control threshold and error ampli- fier compensation node. the trip threshold of ltm4651s current comparator increases with a respective rise in compa voltage. a small filter capacitor ( 10pf) internal to the ltm4651 on this pin introduces a high-frequency roll-off of the error-amplifier response, yielding good noise rejection in the control-loop. compa is usually electrically connected to compb in ones application, thus applying default loop compensation. loop compensation (a series resistor-capacitor) can be applied externally to compa if desired or needed, instead. see compb. compb (e1 ): internal loop compensation network. for a majority of applications, the internal, default loop compensation of the ltm4651 is suitable to apply as is and yields very satisfactory results : apply the default loop compensation to the control loop by simply connecting compa to compb. when more specialized applications require a personal touch to the optimization of control loop response, this can be accomplished by connecting a series resistor-capacitor network from compa to sv out C and leaving compb open circuit. vinreg (d3 ): input voltage regulation programming pin. optionally connect this pin to the midpoint node formed by a resistor-divider between v d and sv out C . when the voltage on vinreg falls below approximately 2v with respect to sv out C , a vinreg control loop servos compa so as to decrease the power inductor current and thus regulate vinreg at 2v with respect to sv out C . see the applications information section. if this input voltage regulation feature is not desired, con - nect vinreg to intv cc . temp + ( j1, j6): temperature sensor, positive input. emitter of a 2n3906-genre pnp bipolar junction transistor (bjt). optionally interface to temperature monitoring cir - cuitry such as ltc ? 2997, ltc2990, ltc2974 or ltc2975. otherwise leave electrically open. pins j1 and j6 are electrically connected together internal to the ltm4651, and thus it is only necessary to connect one temp + pin to monitoring circuitry. the remaining temp + pin can be used for redundant connectivity or routed to an ict test point for design-for-test considerations, as desired. pin functions lt m4651 4651f
10 for more information www.linear.com/ltm4651 simplified block diagram temp C ( j2, j7): temperature sensor, negative input. collector and base of a 2n3906-genre pnp bipolar junc- tion transistor (bjt). optionally interface to temperature monitoring cir cuitr y such as ltc2997, ltc2990, ltc2974 or ltc2975 . otherwise leave electrically open. pins j2 and j7 are electrically connected together internal to the ltm4651 , and thus it is only necessary to connect one temp C pin to monitoring circuitry. the remaining temp C pin can be used for redundant connectivity or routed to an ict test point for design-for-test considerations, as desired. sw (h4): switching node of switching converter stage. used for test purposes. may be routed a short distance with a thin trace to a local test point to monitor switching action of the converter, if desired, but do not route near any sensitive signals; otherwise, leave electrically open circuit. nc ( a6 C 7, b2, b6 C 7, c1, c6 C 7, d6 C 7, e6 C 7, f6 C 7, g6 C 7, h6 C 7, k6 C 7, l6 C 7): no connect pins, i.e., pins with no internal connection. the nc pins predominantly serve to provide improved mounting of the module to the board. in one s layout, nc pins are permitted to remain electrically unconnected or can be connected as desired, e.g., connected to a v out C plane for heat-spreading pur - poses and/or to facilitate routing. pin functions 4651 bd isetb run: >1.2v typ = on <1.07v typ = off 1f c inh sv in m t m b c inl power control and analog circuits pgnd v out ? v in 3.6v to 58v sw pgdfb v out ? gnd compa compb intv cc f set 10pf 1.5nf 10nf 50 v out ? 249k + ? 2v + ? 4.99k 220pf pgood logic v out ? 0.1f 1 400nh 4h temp ? temp + sv out ? 0.1f v in v d 0.1f r iset gnd s n s to current comparators, pwm and fet drivers hi-z when v pgdfb ? sv out ? is within 0.6v 7.5% r pgdfb load-local mlccs (high- frequency decoupling) v out ? up to 0a down to (v in ?58v), no exceeding 26v below pgnd c outh c d 4.7f 2 c dgnd * + error amplifier 50a + ? run (referred to gnd) clkin (referred to gnd) extv cc iseta nc r iset = | v out ? | 50 a 400khz default sv out ? 100 vinreg comp buffer pgood (referred to gnd) (centrally located pnp temp sensor) i l c inout * *c inout and c dgnd optional, for reduced radiated emi. see figures 5 through 8. i svin i svout ? load lt m4651 4651f
11 for more information www.linear.com/ltm4651 test circuit decoupling requirements application symbol parameter conditions min typ max units test circuit 1 c inh , c d external high frequency input capacitor requirement, 24v v in 34v, v out C = C24v 2a 9.4 f c outh external high frequency output capacitor requirement 24v v in 34v, v out C = C24v 2a 22 f t a = 25c. refer to test circuit 1. iseta isetb v in sv in run gnd clkin v d intv cc vinreg compa compb f set pgood pgdfb gnd sns pgnd v out ? sv out ? temp + temp ? extv cc ltm4651 v out ? ?24v up to 2a at v in = 24v c outh 27f load c outl * 68f r pgdfb 196k r fset 57.6k r set 480k c d 4.7 f 2x c inh 4.7 f v in 3.6v to 34v 4651 tc01 + c th 0.1 f r th 499 c extvcc 1f sw nc r extvcc ** 0 *polarized output capacitors c outl , if used, must be rated to withstand ~0.3v typical reverse polarity prior to ltm4651 start-up, stemming from a weakly forward-biased body diode. in such cases, a schottky diode should be connected between pgnd and v out ? to limit the voltage. see the applications information section and figures 33a and 33b. **outside the ate test environment, r extvcc , if used, should not be 0. see the applications information section. lt m4651 4651f
12 for more information www.linear.com/ltm4651 power module description the ltm4651 is a non-isolated switch mode dc/dc power supply. it can provide up to 4a output current with a few external input and output capacitors. set by a single resistor, r set , the ltm4651 regulates a negative output voltage, v out C . v out C can be set to as low as C26.5v to as high as C0.5v. the ltm4651 operates from a positive input supply rail, v in , between 3.6v and 58v. the ltm4651 s safe operating area is defined by : v in + |v out C | 58v. the typical application schematic is shown in figure 32. the output current capability of the ltm4651 is dependent on v in and v out , as indicated in the page 1 graph. though the ltm4651 is a ground-referred buck converter topologyalso known as a two-switch buck- boost converter it contains built-in level-shift circuitry so that the run, clkin, and pgood pins are conveniently referred to gnd (not v out C ). the ltm4651 contains an integrated constant-frequency current mode regulator, power mosfets, power inductor, emi filter and other supporting discrete components. the nominal switching frequency range is from 400khz to 3mhz, and the default operating frequency is 400khz. it can be externally synchronized to a clock, from 250khz to 3mhz. see the applications information section. the ltm4651 supports internal and external control loop compensation. internal loop compensation is selected by connecting the compa and compb pins. using internal loop compensation, the ltm4651 has sufficient stability operation margins and good transient performance with a wide range of output capacitors, even ceramic-only output capacitors. for external loop compensation, see the ap - plications information section. ltpowercad ? is available for transient load step and stability analysis. input filter and noise cancellation circuitry reduces noise- coupling to the modules inputs and outputs, ensuring the module s electromagnetic interference (emi) meets the limits of en55022 class b (see figures 5 to 8). pulling the run pin below 1.2v forces the ltm4651 into a shutdown state. a capacitor can be applied from iseta to sv out C to program the output voltage ramp-rate; or, the default ltm4651 ramp-rate can be set by connecting iseta to isetb ; or, voltage tracking can be implemented by interfacing rail voltages to the iseta pin. see the ap - plication information section. multiphase operation can be employed by applying an external clock sour ce to the ltm4651s synchronization input, the clkin pin. see the typical applications section. ldo losses within the module are reduced by connecting extv cc to pgnd through an rc-filter or by connecting extv cc to a suitable voltage source. the ltm4651 also features a spare control pin called vinreg which can be used to reduce the input current draw during input line sag (brownout) conditions. con - nect vinreg to intv cc when this feature is not needed. lt m4651 4651f
13 for more information www.linear.com/ltm4651 the typical ltm4651 application circuit is shown in test circuit 1. external component selection is primarily deter - mined by the maximum load current and output voltage. refer to t able 8 for recommended external component values. output current capability v aries as a function of v in to v out C conversion ratios the output current capability of the ltm4651 has a strong dependency on the operating input (v in ) and output (v out C ) voltages, as highlighted in the page 1 graph. the reason for this is inherent in the two-switch buck- boost topology employed by the ltm4651 . to protect the primary power mosfet (m t ) from overstress (see simplified block diagram), its peak current (i pk ) is limited by control circuitry to 6a. when m t is on, observe that no current flows to ltm4651s output; furthermore, observe that only when m t is off does current flow to the output of the ltm4651. as a consequence of this arrangement: for a given output voltage, current limit inception activates sooner at low line (higher, larger duty cycle) than at high line (lower, smaller duty cycle). a further consequence is : for a given input voltage, the output power capability of the ltm4651 is higher for lower-magnitude v out C (lower, smaller duty cycle) than for higher-magnitude v out C (higher, larger duty cycle). the combination of these effects is shown the plots in the page 1 graph and described by the following equation: i out(capability) = v in ? i pk C ? i pkCpk 2 ? ? ? ? ? ? ? ? ? v in C v out C (1) where: ?i pk-pk is the inductor ripple current, in amps, and ? (unit less) is the efficiency of the ltm4651. applications information for completeness, ?i pk-pk is given by: where: l is 4h, the ltm4651s power inductor value, and f sw is the switching frequency of the ltm4651, in mhz. for a practical design, ?i pk-pk is designed to be less than ~2a pk-pk . for a practical design, the ltm4651 s on-time of m t each switching cycle should be designed to exceed the ltm4651 control loops specified minimum on-time of 60ns, t on(min) , (guardband to 90ns) i.e.: d f sw > t on(min) (3) where d (unitless) is the duty-cycle of m t , given by: d = Cv out C v in C v out C (4) combining eq. 4 with eq. 1, it can be illustrative to see: i out(capability ) = (1Cd)? i pk C ? i pk Cpk 2 ? ? ? ? ? ? ? ? ? (5) in rare cases where the minimum on-time restriction is violated, the frequency of the ltm4651 automatically and gradually folds back down to one-fifth of its programmed switching frequency to allow v out C to remain in regulation. be reminded of notes 2, 3 and 5 in the electrical char - acteristics section regarding output current guidelines. lt m4651 4651f
14 for more information www.linear.com/ltm4651 applications information input capacitors the ltm4651 achieves low input conducted emi noise due to tight layout and high-frequency bypassing of mosfets m t and m b within the module itself. a small filter induc - tor?(400nh ) is integrated in the input line (from v in to v d ) provides further noise attenuationagain, local to the switching mosfets. the v d and v in pins are available for external input capacitorsv d and v inh to form a high-frequency ? filter. as shown in the simplified block diagram, the ceramic capacitor c d on the ltm4651 s v d pins handles the majority of the rms current into the dc/ dc converter power stage and requires careful selection, for that reason. to meet the radiated emissions requirements of e n55022b, an additional filter capacitor, c inout , is needed connecting from v in to v out C . see figures 5 to 8 for emi performance. the input capacitance, c d , is needed to filter the pulsed current drawn by m t . to prevent excessive voltage sag on v d , a low-effective series resistance (low-esr) input capacitor should be used, sized appropriately for the maximum c d rms ripple current: i cd(rms) = i pk ? d ? (1Cd) (6) i cd(rms) is maximum for d = 1/2. for d = 1/2, i cd(rms) ?=?1/2?? ?i pk or 3a. this simplification of the worst- case condition is commonly used for design purposes because even significant deviations in d do not offer much relief, in practice. furthermore: note that ripple current ratings from capacitor manufacturers are often based on 2000 hours of life; therefore, it is advisable to significantly over-design c d , and/or choose a capacitor rated at a higher temperature than required. err on the side of caution and contact the capacitor manufacturer to understand the capacitor vendors derating methodology. several capacitors may be paralleled to meet the applica - tions target size, height, and c d rms ripple current rating. for lower input voltage applications, sufficient bulk input capacitance is needed for c inl to counteract line sag and transient effects during output load changes. suggested values for c d and c inh are found in table 8. take note that c d is connected from v d to v out C , whereas c inh and c inl are connected from v in to pgnd; this is deliberate. a final precaution regarding ceramic capacitors concerns the maximum input voltage rating of the ltm4651s v in , sv in , and v d pins. a ceramic input capacitor combined with trace or cable inductance forms a high q (underdamped) tank circuit. if the ltm4651 circuit is plugged into a live supply, the input voltage can ring to twice its nominal value, possibly exceeding the devices rating. this situa - tion is easily avoided; see the hot-plugging safely section. output capacitors output capacitors c outh and c outl are applied to v out C of the ltm4651 : sufficient capacitance and low esr are called for, to meet the output voltage ripple, loop stability, and transient requirements. c outl can be a low esr tantalum or polymer capacitor. c outh is a ceramic capacitor. the typical output capacitance is 22f (type x5r material, or better), if ceramic-only output capacitors are used. for highest reliability designs, polarized output capacitors (v outl ) are not recommended, as there is a possibility of a diode-drop of reverse voltage appearing transiently on v out C during rapid application of input voltage or when run is toggled logic high (see figures 33). when polarized capacitors are used on v out C , contact the capacitor vendor to understand what reverse voltage their polarized capaci - tor can withstand. be advised, polarized capacitor reverse voltage rating is sometimes temperature-dependent. output voltage ripple ( ?v out(pk-pk) C ) is governed by charge lost in c outh and c outl while m t is on, in addition to the contribution of a resistive drop across the esr of the output capacitors. this is expressed by: ? v out(pkCpk) i load ?d c out ? f sw + i load ?esr d (7) table 8 shows a matrix of suggested output capacitors optimized for transient step-loads that are 50% of the full load capability for that combination of v in , v out C , and f sw . the table optimizes total equivalent esr and total bulk capacitance to yield the stated transient-load performance. additional output filtering may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. the ltpowercad design tool is available for transient and stability analysis. lt m4651 4651f
15 for more information www.linear.com/ltm4651 applications information forced continuous operation leave the clkin pin open circuit to command the ltm4651 for forced continuous operation. in this mode, the control loop is allowed to command the inductor peak current to approximately C1a, allowing for significant negative average current. clocking the clkin pin at a frequency within 40% of the target switching frequency commanded by the f set pin synchronizes m t s turn-on to the rising edge of the clkin pin. output voltage programming, tracking and soft-start the ltm4651 regulates its output voltage, v out C , according to the differential voltage present across iseta and sv out C . in most applications, the output voltage is set by simply con - necting a resistor, r set , from iseta to sv out C , according to : r set = Cv out C 50a (8) since the ltm4651 control loop servos its output volt - age according to the voltage between iseta and sv out C : placing a capacitor, c ss , parallel to r set configures the ramp-up rate of iseta and thus v out C . in the time domain, the output voltage ramp-up after the run pin is toggled from low to high (t = 0s) is given by: v out (t) C = i iseta ?r set ? 1C e C t r set ?c set ? ? ? ? ? ? ? ? ? ? ? ? ? ? (9) the soft-start time, t ss , is defined as the time it takes for v out C to ramp from 0v to 90% of its final value: t ss = Cr set ?c set ?in(1C 0.9) (10) or t ss = 2.3 ? r set ?c set (11) a default value of c set = 1.5nf can be implemented by connecting iseta to isetb. for other ramp-up rates, con - nect an external c set capacitor parallel to r set . when starting up into a pre-biased v out C , the ltm4651 stays in a sleep mode, keeping m t and m b off until v iseta equals v gndsns after which, the dc/dc converter com- mences switching action and v out C is ramped according to the voltage commanded by iseta. since the ltm4651 control loop servos its gnd sns voltage to match that of iseta s, the ltm4651s output can be configured to track any voltage applied to iseta, referenced to sv out C . the ltm4651 can track the mirror-image of a positive rail to generate the negative half of a split-supply, as seen in figure 37. optional diodes to guard against overstress just prior to output voltage start-up, a mechanism exists whereby a diode-drop of reverse polarity can appear on v out C . see the simplified block diagram and observe : just prior to output voltage start-up, sv in bias current (i svin ) flows through the modules control ic, to sv out C ; from there, the bias current (now i svout C ) flows into v out C and through m b s body diode, to sw. this current (now i l ) continues to flowthough the 4h power inductorto pgnd and ground, closing the control ic bias circuit s path. it is this current through m b s body diode that cre - ates a diode-drop of reverse polarity (positive voltage) on v out C , as shown in figure 33. the voltage excursion is highest when run toggles high because that is the instant when intv cc powers-up, with a corresponding increase in i svin /i svout C /i l current flow. with higher current flow, the forward voltage drop (v f ) of m b s body diodeand thus, the positive voltage excursion on v out C is higher. if this transient voltage excursion is unwelcome for the load or polarized output capacitors, minimize it with a low?v f schottky diode that straddles v out C and pgnd (see figure?32 circuit and figure 33 performance). addition - ally, the voltage excursion can be empirically reduced by increasing output capacitance. lastly : in applications where it is anticipated that v in may be rapidly applied (e.g., <10s) and c inout is used, the resulting capacitor-divider network formed by c inout and c inl ||c inh may transiently drag v out C positive. it is recom - mended to apply a low v f schottky diode from v out C to pgnd, in such applications. the reverse mechanism ap - plies, as well: in applications where it is anticipated that lt m4651 4651f
16 for more information www.linear.com/ltm4651 v in may be rapidly discharged and c inout is used, the resulting capacitor-divider network formed by c inout and c inl || c inh may transiently drag v out C excessively negative. it is recommended to straddle v out C and pgnd with a tvs diode, if output voltage excursions during v in -discharge are anticipated. frequency adjustment the default switching frequency (f sw ) of the ltm4651 is 400khz. this is suitable for mainly low-v in or low-v out C applications (v in < 5v or |v out C | < 5v ). for a practical design, the ltm4651 s inductor ripple current (? pk-pk ) is suggested to be less than ~2a pk-pk . from eq. 2, it follows that f sw should be chosen such that: 1 l ?i pk-pk 1 v in ? 1 v out ? ? ? ? ? ? ? ? ? ? ? (12 ) in some cases, the value of f sw yielded by eq. 12 violates the supported minimum on time of the ltm4651 (see eq.?3). if this occurs, choose f sw instead according to: f sw < d t on(min) (13) the primary consequence of using a lower switching frequency than that dictated by eq. 12 is that the output current capability of the ltm4651 is reduced, according to eq. 5. to configure the ltm4651 for a higher switching frequency than 400khz default, apply a resistor, r fset , between the f set pin and sv out C . r fset is given (in m?) by: r fset (m?) = 1 10pf ?[f sw (mhz)C 0.4(mhz)] (14) the relationship of r fset to programmed f sw is shown in figure 2. see table 1 and table 8 for recommended f sw and as - sociated r fset values for various combinations of v in and v out C . applications information figure 2. relationship between r fset and target f sw v out C (v) v in (v) C0.5 C3.3 C5 C8 C12 C15 C20 C24 3.6 400khz, no r fset 400khz, no r fset 400khz, no r fset 400khz, no r fset 400khz, no r fset 400khz, no r fset 425khz, 4.3m? 450khz , 2.2m? 5 450khz, 2.2m? 475khz , 1.3m? 500khz, 1m? 525khz, 806k? 550khz, 665k? 12 550khz, 665k? 700khz, 332k? 825khz, 237k? 875khz, 210k? 900khz, 200k? 1mhz, 165k? 24 drive clkin with a 200khz clock, no r fset 450khz, 2.2m? 600khz , 499k? 800khz , 249k? 1.1mhz , 143k? 1.2mhz, 124k? 1.4mhz, 100k? 1.5mhz, 90.9k? 36 not recommended due to on- time criteria violation 500khz, 1m? 850khz , 221k? 1.2mhz , 124k? 1.4mhz, 100k? 1.6mhz, 82.5k? n/a 48 900khz, 200k? n/a due to soa criteria violation table 1. recommended switching frequency (f sw ) and r fset values for common combinations of v in and v out C lt m4651 4651f 10 programmed switching frequency (mhz) 4651 f02 rf set not used rf set (k) 10 100 1k 10k 0.1 1
17 for more information www.linear.com/ltm4651 power module protection the ltm4651 s current mode control architecture provides fast cycle-by-cycle current limit in an overcurrent condi - tion, as shown in the typical performance characteristics section. if the output voltage collapses sufficiently due to an overload or short-circuit condition, minimum on-time will be violated (eq. 3) and the internal oscillator will then fold-back automatically to one-fifth of the ltm4651s programmed switching frequencyhereby reducing the output current and affording the load a chance to recover. the ltm4651 features input overvoltage shutdown protection: when v in +|v out C | > 68v , switching action ceases (with 4v of hysteresis) however, be advised that this protection is only active outside the ltm4651s safe operating area (see note 1 and note 4 of the electrical characteristics table). the ltm4651 ceases switching action if internal tempera - tures exceed 165c. the control ic resumes operation after a 10c cool-down hysteresis. note that these typical parameters are based on measurements in a lab oven and are not production tested. this overtemperature protection is intended to protect the device during momentary over - load conditions. the maximum rated junction temperature will be exceeded when this overtemperature protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. the lt m4651 does not feature any specialized output overvoltage protection beyond what is inherent to the control loops servo mechanism. run pin enable the run pin is used to enable the power module or se - quence the power module. the threshold is 1.2v. the run pin can be used to provide an under voltage lockout (uvlo) function by connecting a resistor divider from the input supply to the run pin, as shown in figure 3. undervoltage lockout keeps the ltm4651 in shutdown until the supply input voltage is above a certain voltage programmed by the user. the run pin hysteresis voltage prevents noise from falsely tripping uvlo. resistors are chosen by first selecting r b (refer to figure 3). then: r a = r b ? v in(on) 1.2v C 1 ? ? ? ? ? ? ? ? ? ? (15) where v in(on) is the input voltage at which the undervolt - age lockout is overcome and the supply turns on. r a may be replaced with a hardwired connection from v d to run. the v in turn-off voltage, v in(off) is given by: v in(off) = 1.07v ? r a r b +1 ? ? ? ? ? ? ? ? ? ? (16) if uvlo is not needed, run can be connected to ltm4651 s v d or v in pins. when run is below its threshold, uvlo is engaged, m t and m b are turned off, intv cc ceases to be regulated, and iseta is discharged to sv out C by internal circuitry. loop compensation external loop compensation may be preferred for some applications and can be implemented easily, as follows : leave compb open circuit ; connect a series-r c network (r th and c th ) from compa to sv out C ; in some instances, connect a capacitor (c thp ) from compa to sv out C (par - alleling the r th-cth series-r c network). see table 8 for suggested input and output capacitances for a variety of operating conditions. additionally, the ltpowercad design tool is available for transient and stability analysis. applications information figure 3. undervoltage lockout resistive divider run pin r a r b v supply 4651 f03 lt m4651 4651f
18 for more information www.linear.com/ltm4651 hot-plugging safely the small size, robustness and low impedance of ceramic capacitors make them an attractive option for the input bypass capacitors (c d and c inh ) of the ltm4651 . however, these capacitors can cause problems if the ltm4651 is plugged into a live supply (see linear technology ap - plication note 88 for a complete discussion). the low loss ceramic capacitor combined with stray inductance in series with the power source forms an under damped tank cir cuit, and the voltage at the v in pin of the ltm4651 can ring to twice the nominal input voltage, possibly ex - ceeding the ltm4651s rating and damaging the part. if the input supply is poorly controlled or the user will be plugging the ltm4651 into an energized supply, the input network should be designed to prevent this overshoot by introducing a damping element into the path of current flow. this is often done by adding an inexpensive elec - trolytic bulk capacitor (c inl ) across the input terminals of the ltm4651. the selection criteria for c inl calls for: an esr high enough to damp the ringing; a capacitance value several times larger than c inh . c inl does not need to be located physically close to the ltm4651; it should be located close to the application board s input connec - tor, instead. intv cc and extv cc connection when run is logic high, an internal low dropout regula - tor regulates an internal supply, intv cc , that powers the control circuitry for driving ltm4651 s internal mosfets. intv cc is regulated at 3.3v above v out C . in this manner, the ltm4651 s intv cc is directly powered from sv in , by default. the gate driver current through the ldo is about 20ma for a typical 1mhz application. the internal ldo power dissipation can be calculated as: p ldo_loss(intvcc) = 20ma ?(sv in + | v out C | C3.3v) (17) the ldo draws current off of extv cc instead of sv in when extv cc is tied to a voltage higher than 3.2v above v out C and sv in is 5v above v out C . for output voltages at or below C4v , this pin can be connected to pgnd through an rc- filter. when the internal ldo derives power from extv cc instead of sv in , the internal ldo power dissipation is: p ldo_loss(extvcc) = 20ma ?(| v out C | C3v) (18) the recommended value of the resistor between pgnd and extv cc is roughly |v out C | ? 4 /v. this resistor, r extvcc , must be rated to continually dissipate (0.02a) 2 ? r extvcc . the primary purpose of this resistor is to prevent extv cc overstress under a fault condition. for example, when an inductive short-circuit is applied to the module s output, v out C may be briefly dragged above extv cc forward- biasing the v out C -to-extv cc body diode. this resistor limits the magnitude of current flow into extv cc . bypass extv cc to v out C with 1f of x5r (or better) mlcc. multiphase operation multiple ltm4651 devices can be paralleled for higher output current applications. for lowest input and output voltage and current ripples, it is advisable to synchronize paralleled ltm4651 s to an external clock (within 40% of the target switching frequency set by f set see test circuit?1). see figure 34 for an example of a synchroniz - ing circuit. lt m4651 modules can be paralleled without synchronizing circuits: just be aware that some beat-frequency ripple will be present in the output voltage and reflected input current by virtue of the fact that such modules are not operating at identical, synchronized switching frequencies. the ltm4651 device is an inherently current mode con - trolled device, so parallel modules will have good current sharing s shown in figure 35. this helps balance the thermals on the design. to parallel ltm4651s, connect the respective compa, iseta, and gnd sns pins of each ltm4651 together to share the current evenly. in addition, tie the respective run pins of paralleled ltm4651 devices together, to ensure proper start-up and shutdown behavior. figure 34 shows a schematic of ltm4651 devices operating in parallel. note that for parallel applications, eq. 8 becomes: r set = Cv out C 50a ?n (19) applications information lt m4651 4651f
19 for more information www.linear.com/ltm4651 where n is the number of ltm4651 modules in parallel configuration. depending on the duty cycle of operation (eq. 4), the output voltage ripple achieved by paralleled, synchronized ltm4651 modules may be considerably smaller than what is yielded by eq. 7. application note 77 provides a detailed explanation of multiphase operation (relevant to parallel ltm4651 applications) pertaining to noise reduction and output and input ripple current cancellation. regardless of ripple current cancellation, it remains important for the output capacitance of paralleled ltm4651 applications to be designed for loop stability and transient response. ltpowercad is available for such analysis. figure 4 illustrates the rms ripple current reduction as a function of the number of interleaved (paralleled and synchronized) ltm4651 modules derived from ap - plication note 77. radiated emi noise the generation of radiated emi noise is an inherent disad - vantage of switching regulators. fast switching turn-on and turn-off of the power mosfet s necessary for achieving high efficiencycreate high-frequency ( ~30mhz+) ?l/?t changes within dc/dc converters. this activity tends to be the dominant source of high-frequency emi radiation in such systems. the high level of device integration within ltm4651 including optimized gate-driver and critical front-end ? filter inductordelivers low radiated emi noise performance. figures 5 to 8 show typical ex - amples of ltm4651 meeting the radiated emission limits established by en55022 class b. thermal considerations and output current derating the thermal resistances reported in the pin configuration section of this data sheet are consistent with those pa - rameters defined by je sd51 -12 and are intended for use with finite element analysis (fea) software modeling tools that leverage the outcome of thermal modeling, simula - tion, and correlation to hardware evaluation performed on a module package mounted to a hardware test board. the motivation for providing these thermal coefficients is found in je sd51 -12 (guidelines for reporting and using electronic package thermal information). many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the module regulator s thermal performance in their appli - cation at various electrical and environmental operating conditions to compliment any fea activities. without fea software, the thermal resistances reported in the pin con - figuration section are, in and of themselves, not relevant to providing guidance of thermal per formance ; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to ones application-usage, and can be adapted to correlate thermal performance to ones own application. the pin configuration section gives four thermal coeffi - cients explicitly defined in jesd51-12; these coefficients are quoted or paraphrased below : 1. ja , the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclo - sure. this environment is sometimes referred to as still air although natural convection causes the air to move. this value is determined with the part mounted to a jesd51 -9 defined test board, which does not reflect an actual application or viable operating condition. 2. jcbottom , the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. in the typical module regulator, the bulk of the heat flows out the bottom of the pack - age, but there is always heat flow out into the ambient environment. as a result, this thermal resistance value may be useful for comparing packages but the test conditions don t generally match the users application. 3. jctop , the thermal resistance from junction to top of the product case, is determined with nearly all of the applications information lt m4651 4651f
20 for more information www.linear.com/ltm4651 applications information figure 4. normalized input rms ripple current vs duty cycle for one to six ltm4651s (phases) figure 6. radiated emissions scan of the ltm4651 producing C24v out at 2a, from 25v in . dc2328 hardware. f sw = 1.2mhz. measured in a 10m chamber. peak detect method figure 5. radiated emissions scan of the ltm4651. producing C24v out at 1a, from 12v in . dc2328a hardware. f sw = 1.2mhz. measured in a 10m chamber. peak detect method 0.75 0.8 4651 f04 0.70.650.60.550.50.450.40.350.30.250.20.150.1 0.85 0.9 duty cycle ( ?v out ? / v in ? v out ? ) 0 dc load current rms input ripple current 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 1-phase 2-phase 3-phase 4-phase 6-phase figure 8. radiated emissions scan of the ltm4651. producing C12v out at 2a, from 12v in . dc2328a hardware. f sw = 700khz. measured in a 10m chamber. peak detect method figure 7. radiated emissions scan of the ltm4651. producing C24v out at 2a, from 34v in . dc2328a hardware. f sw = 1.2mhz. measured in a 10m chamber. peak detect method lt m4651 4651f amplitude (dbv/m) 50 60 70 40 30 20 10 ?10 0 frequency (mhz) 30 830 130 230 330 430 530 630 730 930 1000 4651 f05 [1] horizontal [2] vertical qpk limit formal meas dist 10m spec dist 10m + amplitude (dbv/m) 50 60 70 40 30 20 10 ?10 0 frequency (mhz) 30 830 130 230 330 430 530 630 730 930 1000 4651 f06 [1] horizontal [2] vertical qpk limit formal meas dist 10m spec dist 10m + amplitude (dbv/m) 50 60 70 40 30 20 10 ?10 0 frequency (mhz) 30 830 130 230 330 430 530 630 730 930 1000 4651 f07 [1] horizontal [2] vertical qpk limit formal meas dist 10m spec dist 10m + amplitude (dbv/m) 50 60 70 40 30 20 10 ?10 0 frequency (mhz) 30 830 130 230 330 430 530 630 730 930 1000 4651 f08 [1] horizontal [2] vertical qpk limit formal meas dist 10m spec dist 10m +
21 for more information www.linear.com/ltm4651 component power dissipation flowing through the top of the package. as the electrical connections of the typical module regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. as in the case of jcbottom , this value may be useful for comparing packages but the test conditions dont generally match the users application. 4. jb , the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resis - tance where almost all of the heat flows through the bottom of the module regulator and into the board, and is really the sum of the jcbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. the board temperature is measured a specified distance from the package, using a two sided, two layer board. this board is described in jesd51-9. a graphical representation of the aforementioned ther - mal resistances is given in figure 9; blue resistances are contained within the module regulator, whereas green resistances are external to the module package. as a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by je sd51 -12 or provided in the pin configuration section replicates or conveys normal operating conditions of a module regulator. for example, in normal board-mounted applications, never does 100% of the devices total power loss (heat) thermally conduct exclusively through the top or exclusively through bot - tom of the module packageas the standard defines for jctop and jcbottom , respectively. in practice, power loss is thermally dissipated in both directions away from the package granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. within the ltm4651, be aware there are multiple power devices and components dissipating power, with a con - sequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. to reconcile this complication without sacrificing modeling simplicity but also not ignoring practical realities an approach has been taken using fea software modeling along with laboratory testing in a controlled-environment chamber to reason - ably define and correlate the thermal resistance values supplied in this data sheet : (1) initially, fea software is used to accurately build the mechanical geometry of the ltm4651 and the specified pcb with all of the correct material coefficients along with accurate power loss sour ce definitions ; (2) this model simulates a software- defined jedec environment consistent with jesd51 -9 and jesd51 -12 to predict power loss heat flow and temperature readings at different inter faces that enable the calculation of the jedec-defined thermal resistance values ; (3) the model and fea software is used to evaluate the ltm4651 with heat sink and airflow ; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated applications information figure 9. graphical representation of jesd51-12 thermal coefficients 4651 f09 module device junction-to-case (top) resistance junction-to-board resistance junction-to-ambient thermal resistance components case (top)-to-ambient resistance board-to-ambient resistance junction-to-case (bottom) resistance junction ambient case (bottom)-to-board resistance lt m4651 4651f
22 for more information www.linear.com/ltm4651 conditions with thermocouples within a controlled envi- ronment chamber while operating the device at the same power loss as that which was simulated. the outcome of this process and due diligence yields the set of derating cur ves provided in later sections of this data sheet, along with well-correlated je sd51- 12-defined values provided in the pin configuration section of this data sheet. the C 5v , C 15v and C 24v power loss curves in figures?10, 11 and 12 respectively can be used in coordination with the load current derating curves in figures 13 to 30 for calculating an approximate ja thermal resistance for the lt m4651 with various heat sinking and air flow conditions. these thermal resistances represent demonstrated performance of the lt m4651 on dc2328 a hardware ; a 4- layer f r4 pcb measuring 99mm 133mm 1.6mm using outer and inner copper weights of 2oz and 1oz , respectively. the power loss curves are taken at room temperature, and are increased with multiplicative factors with ambient temperature. these approximate factors are listed in table 2. (compute the factor by interpolation, for intermediate tem peratures.) the derating curves are plotted with the lt m4651 s output initially sourcing its maximum output capability (see eq. 5) and the ambient temperature at 30 c. the output voltages are C 5v , C 15v and C 24v . these are chosen to include the lower and higher output voltage ranges for correlating the thermal resistance. in all derat - ing curves, the switching frequency of operation follows guidance provided by t able 1. thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. the junction temperatures are monitored while ambient temperature is increased with and without air flow, and with and without a heat sink attached with thermally conductive adhesive tape. the power loss increase with ambient temperature change is factored into the derating curves. the junctions are maintained at 120 c maximum while lowering output current or power while increasing ambient temperature. the decreased output current decreases the internal module loss as ambient temperature is increased. the monitored junction temperature of 120 c minus the ambient operating temperature specifies how much module temperature rise can be allowed. as an example in figure 26, the load current is derated to 1a at 60c a m bient with 200lfm airflow and no heat sink and the room temperature ( 25 c ) power loss for this 12v in to C24v out at 1a out condition is 3.55w . a 3.9w loss is calculated by multiplying the 3.55w room temperature loss from the 12v in to C 24v out power loss curve at 1a (figure 12), with?the 1.1 multiplying factor at 60 c ambient (from table 2). if the 60 c ambient temperature is subtracted from the 120 c junction temperature, then the difference of 60 c divided by 3.9w yields a thermal resistance, ja , of 15. 4c /w in good agreement with table 4. tables 3, 4 and 5 provide equivalent thermal resistances for C 5v , C 15v and C 24v outputs with and without air flow and heat sinking. the derived thermal resistances in tables 3, 4 and 5 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. room temperature power loss can be derived from the efficiency curves in the typical performance characteristics section and adjusted with ambient temperature multiplicative factors from table 2. table 2. power loss multiplicative factors vs ambient temperature ambient temperature power loss multiplicative factor up to 40c 1.00 50c 1.05 60c 1.10 70c 1.15 80c 1.20 90c 1.25 100c 1.30 110c 1.35 120c 1.40 applications information lt m4651 4651f
23 for more information www.linear.com/ltm4651 table 3. C5v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 13, 14, 15 5, 12, 24 figure 10 0 none 20.8 figures 13, 14, 15 5, 12, 24 figure 10 200 none 17.0 figures 13, 14, 15 5, 12, 24 figure 10 400 none 16.3 figures 16, 17, 18 5, 12, 24 figure 10 0 bga heat sink 18.7 figures 16, 17, 18 5, 12, 24 figure 10 200 bga heat sink 16.1 figures 16, 17, 18 5, 12, 24 figure 10 400 bga heat sink 14.2 table 4. C15v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 19, 20, 21 5, 12, 24 figure 11 0 none 20.0 figures 19, 20, 21 5, 12, 24 figure 11 200 none 16.6 figures 19, 20, 21 5, 12, 24 figure 11 400 none 14.4 figures 22, 23, 24 5, 12, 24 figure 11 0 bga heat sink 19.0 figures 22, 23, 24 5, 12, 24 figure 11 200 bga heat sink 14.2 figures 22, 23, 24 5, 12, 24 figure 11 400 bga heat sink 12.6 table 5. C24v output derating curve v in (v) power loss curve airflow (lfm) heat sink ja (c/w) figures 25, 26, 27 5, 12, 24 figure 12 0 none 18.3 figures 25, 26, 27 5, 12, 24 figure 12 200 none 15.2 figures 25, 26, 27 5, 12, 24 figure 12 400 none 14.4 figures 28, 29, 30 5, 12, 24 figure 12 0 bga heat sink 17.6 figures 28, 29, 30 5, 12, 24 figure 12 200 bga heat sink 14.7 figures 28, 29, 30 5, 12, 24 figure 12 400 bga heat sink 13.9 table 6. heat sink manufacturer (thermally conductive adhesive tape pre-attached) heat sink manufacturer part number website cool innovations 3-0504035ut411 www.coolinnovations.com table 7. thermally conductive adhesive tape vendor thermally conductive adhesive tape manufacturer part number website chomerics t411 www.chomerics.com applications information lt m4651 4651f
24 for more information www.linear.com/ltm4651 applications information table 8. ltm4651 output voltage response vs component matrix. performance of figure 32 circuit with values here indicated, compa connected to compb, c extvcc = 1f, and the following components not used: c th , r th and c outl . load-stepping from 50% of full scale (f.s.) to 100% of f.s. load current, in 1s. typical measured values c outh vendors? part number? c in /c d vendors? part number? avx 12066d107mat2a (100f, 6.3v, 1206 case size) murata grm32er71k475m (4.7f, 80v, 1210 case size) murata grm31cr60j107m (100f, 6.3v, 1206 case size) avx 12065c475mat2a (4.7f, 50v, 1206 case size) taiyo yuden jmk316bbj107mlht (100f, 6.3v, 1206 case size) murata grm31cr71h475m (4.7f, 50v, 1206 case size) tdk c3216x5r0j107m (100f, 6.3v, 1206 case size) taiyo yuden umk316ab7475ml (4.7f, 50v, 1206 case size) avx 1210yd476mat2a (47f, 16v, 1210 case size) tdk c3216x5r1h475m (4.7f, 50v, 1206 case size) murata grm32er61c476m (47f, 16v, 1210 case size) taiyo yuden emk325bj476mm (47f, 16v, 1210 case size) avx 12103d226mat2a (22f, 25v, 1210 case size) taiyo yuden tmk325bj226mm (22f, 25v, 1210 case size) tdk c3225x5r1e226m (22f, 25v, 1210 case size) avx 12105d106mat2a (10f, 50v, 1210 case size) murata grm32er61h106m (10f, 50v, 1210 case size) taiyo yuden umk325bj106m (10f, 50v, 1210 case size) tdk c3225x5r1h106m (10f, 50v, 1210 case size) v out C (v) v in (v) f . s. load (a) c in (v in C to gnd bypass cap) c inout (v in C to v out C bypass cap) c d (v d C to v out C bypass cap) cdgnd (v d C to gnd bypass cap) c outh (ceramic output cap) r iset (k) r pgdfb (k) f sw (khz) r fset (k) r extvcc () load step transient droop (mv) load step pk-pk deviation (mv) recover y time (s) C0.5 5 3.2 4.7f 4.7f 4.7f 4.7f 100f 4 10 n/a 400 n/a 2.2 75 150 55 C0.5 12 4 4.7f 4.7f 4.7f 4.7f 100f 4 10 n/a 400 n/a 2.2 90 190 60 C0.5* 24 4 4.7f 4.7f 4.7f 4.7f 100f 4 10 n/a 200* n/a 2.2 90 190 60 C3.3 5 2.2 4.7f 4.7f 4.7f 4.7f 100f 66.5 22.6 400 n/a 15 65 130 25 C3.3 12 3.5 4.7f 4.7f 4.7f 4.7f 100f 2 66.5 22.6 400 n/a 15 165 330 50 C3.3 24 4 4.7f 4.7f 4.7f 4.7f 100f 2 66.5 22.6 450 2200 15 175 355 50 C3.3 36 4 4.7f 4.7f 4.7f 4.7f 100f 2 66.5 22.6 500 1000 15 160 310 40 C3.3 48 4 4.7f 4.7f 4.7f 4.7f 100f 2 66.5 22.6 500 1000 15 152 300 35 C5 5 1.75 4.7f 4.7f 4.7f 4.7f 47f 2 100 36.5 400 n/a 20 125 235 45 C5 12 3.2 4.7f 4.7f 4.7f 4.7f 47f 2 100 36.5 550 665 20 175 340 60 C5 24 3.85 4.7f 4.7f 4.7f 4.7f 47f 2 100 36.5 600 499 20 185 380 55 C5 36 4 4.7f 4.7f 4.7f 4.7f 47f 2 100 36.5 600 499 20 180 360 45 C5 48 4 4.7f 4.7f 4.7f 4.7f 47f 2 100 36.5 600 499 20 165 330 38 C8 5 1.2 4.7f 4.7f 4.7f 4.7f 47f 160 61.9 450 2200 32.4 125 235 30 C8 12 2.3 4.7 f 4.7f 4.7f 4.7f 47f 160 61.9 700 332 32.4 185 340 30 C8 24 3.1 4.7f 4.7f 4.7f 4.7f 47f 160 61.9 800 249 32.4 180 330 27 C8 36 3.4 4.7f 4.7f 4.7f 4.7f 47f 160 61.9 850 221 32.4 205 400 27 C8 48 3.6 4.7f 4.7f 4.7f 4.7f 47f 160 61.9 900 200 32.4 185 370 25 C12 5 0.9 4.7f 4.7f 4.7f 4.7f 22f 240 95.3 475 1300 49.9 140 270 32 C12 12 1.9 4.7f 4.7f 4.7f 4.7f 22f 240 95.3 825 237 49.9 157 290 25 C12 24 2.75 4.7f 4.7f 4.7f 4.7f 22f 240 95.3 1100 143 49.9 170 325 25 C12 36 3.2 4.7f 4.7f 4.7f 4.7f 22f 240 95.3 1200 124 49.9 200 400 25 C15 5 0.75 4.7f 4.7f 4.7f 4.7f 22f 301 121 500 1000 60.4 90 170 25 C15 12 1.75 4.7f 4.7f 4.7f 4.7f 22f 301 121 875 210 60.4 200 380 32 C15 24 2.5 4.7f 4.7f 4.7f 4.7f 22f 301 121 1200 124 60.4 205 400 28 C15 36 3 4.7f 4.7f 4.7f 4.7f 22f 301 121 1400 100 60.4 210 415 28 C24 5 0.55 4.7f 4.7f 4.7f 2 4.7f 2 10f 2 481 196 550 665 100 105 220 45 C24 12 1.25 4.7f 4.7f 4.7f 2 4.7f 2 10f 2 481 196 1000 165 100 140 275 30 C24 24 2 4.7f 4.7f 4.7f 2 4.7f 2 10f 2 481 196 1500 90.9 100 140 280 27 *to avoid violating minimum on-time criteria, drive clkin with a 200khz, 50% duty cycle clock. consider using ltc6908-1, for example. lt m4651 4651f
25 for more information www.linear.com/ltm4651 figure 16. 5v to C5v derating curve, with bga heat sink figure 17. 12v to C5v derating curve, with bga heat sink figure 18. 24v to C5v derating curve, with bga heat sink applications information derating curves figure 10. C5v out power loss curve figure 11. C15v out power loss curve figure 12. C24v out power loss curve figure 14. 12v to C5v derating curve, no heat sink figure 13. 5v to C5v derating curve, no heat sink figure 15. 24v to C5v derating curve, no heat sink see table 1 for f s w. lt m4651 4651f 1 120 0 0.35 0.70 1.05 1.40 1.75 2.10 2.45 2.80 1.5 3.15 3.50 3.85 maximum load current (a) 4651 f15 0lfm 200lfm 400lfm ambient temperature (c) 20 2 40 60 80 100 120 0 0.22 0.44 0.66 0.88 2.5 1.09 1.31 1.53 1.75 maximum load current (a) 4651 f16 0lfm 200lfm 400lfm ambient temperature (c) 3 20 40 60 80 100 120 0 0.4 0.8 1.2 3.5 1.6 2.0 2.4 2.8 3.2 maximum load current (a) 4651 f17 0lfm 200lfm 400lfm 4 ambient temperature (c) 20 40 60 80 100 120 0 0.35 0.70 0 1.05 1.40 1.75 2.10 2.45 2.80 3.15 3.50 3.85 maximum load current (a) 0.5 4651 f18 0lfm 200lfm 400lfm ambient temperature (c) 20 40 60 80 100 1.0 120 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 maximum load current (a) 5v in , 400khz 1.5 4651 g13 2.0 2.5 3.0 3.5 4.0 4.5 power loss (w) 4651 f10 5v in , 500khz 12v in , 550khz 12v in , 875hz 24v in , 1.2mhz 36v in , 1.4mhz load current (a) 0 0.5 1 1.5 2 2.5 24v in , 600khz 3 0 1 2 3 4 5 6 7 power loss (w) 36v in , 600khz 4651 f11 5v in , 550khz 12v in , 1mhz 24v in ,1.5mhz load current (a) 0 0.5 1 1.5 2 48v in , 600khz 0 1 2 3 4 5 6 7 power loss (w) 4651 f12 load current (a) 0lfm 200lfm 400lfm ambient temperature (c) 20 40 60 80 100 120 0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 maximum load current (a) 0.5 4651 f14 0lfm 200lfm 400lfm ambient temperature (c) 20 40 60 80 100
26 for more information www.linear.com/ltm4651 figure 20. 12v to C15v derating curve, no heat sink figure 19. 5v to C15v derating curve, no heat sink figure 21. 24v to C15v derating curve, no heat sink figure 23. 12v to C15v derating curve, with bga heat sink figure 22. 5v to C15v derating curve, with bga heat sink figure 24. 24v to C15v derating curve, with bga heat sink figure 25. 5v to C24v derating curve, no heat sink figure 26. 12v to C24v derating curve, no heat sink figure 27. 24v to C24v derating curve, no heat sink applications information derating curves see table 1 for f s w. lt m4651 4651f 100 1.75 maximum load current (a) 4651 f23 0lfm 200lfm 400lfm ambient temperature (c) 20 40 60 120 80 100 120 0 0.25 0.50 0.75 1.00 1.25 1.50 0 1.75 2.00 2.25 2.50 maximum load current (a) 4651 f24 0lfm 200lfm 400lfm ambient temperature (c) 0.125 20 40 60 80 100 120 0 0.05 0.10 0.15 0.250 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 maximum load current (a) 4651 f25 0.375 0lfm 200lfm 400lfm ambient temperature (c) 20 40 60 80 100 120 0.500 0 0.125 0.250 0.375 0.500 0.625 0.750 0.875 1.000 1.125 0.625 1.250 maximum load current (a) 4651 f26 0lfm 200lfm 400lfm ambient temperature (oc) 20 40 60 0.750 80 100 120 0 0.25 0.50 0.75 1.00 1.25 1.50 maximum load current (a) 1.75 2.00 maximum load current (a) 4651 f27 0lfm 4651 f19 0lfm 200lfm 400lfm ambient temperature (c) 20 40 60 80 100 200lfm 120 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 maximum load current (a) 400lfm 4651 f20 0lfm 200lfm 400lfm ambient temperature (c) 20 40 60 80 100 ambient temperature (c) 120 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 20 2.25 2.50 maximum load current (a) 4651 f21 0lfm 200lfm 400lfm ambient temperature (c) 20 40 40 60 80 100 120 0 0.125 0.250 0.375 0.500 0.625 60 0.750 maximum load current (a) 4651 f22 0lfm 200lfm 400lfm ambient temperature (c) 20 40 60 80 80 100 120 0 0.25 0.50 0.75 1.00 1.25 1.50
27 for more information www.linear.com/ltm4651 figure 28. 5v to C24v derating curve, with bga heat sink figure 29. 12v to C24v derating curve, with bga heat sink figure 30. 24v to C24v derating curve, with bga heat sink applications information derating curves applications information safety considerations the ltm4651 does not provide galvanic isolation from v in to v out C . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect the unit from catastrophic failure. the fuse or circuit breaker, if used, should be selected to limit the current to the regulator in case of a m t mosfet fault. if m t fails, the system s input supply will source very large currents to pgnd through m t . this can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. a fuse or circuit breaker can be used as a secondary fault protector in this situation. the ltm4651 does feature overcurrent and overtemperature protection. layout checklist/example the high integration of ltm4651 makes the pcb board layout straightforward. however, to optimize its electrical and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for high current paths, including v in , pgnd and v out C . doing so helps to minimize the pcb conduction loss and thermal stress. ? place high frequency ceramic input and output (and, if used, input-to-output) capacitors next to the v in , v d , pgnd and v out C pins to minimize high frequency noise. ? place a dedicated power ground layer underneath the ltm4651. ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. ? do not put vias directly on pads, unless they are capped or plated over. ? use a separate sv out C copper plane for components connected to signal pins. connect sv out C to v out C directly under the module. ? for parallel module applications, connect the v out C , gnd sns , run, iseta, compa and pgood pins together as shown in figure 41. ? bring out test points on the signal pins for monitoring. figure 31 gives a good example of the recommended ltm4651 layout. lt m4651 4651f 100 120 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0lfm 0.40 0.45 0.50 0.55 maximum load current (a) 4651 f28 0lfm 200lfm 400lfm ambient temperature (c) 200lfm 20 40 60 80 100 120 0 0.125 0.250 0.375 400lfm 0.500 0.625 0.750 0.875 1.000 1.125 1.250 maximum load current (a) 4651 f29 0lfm ambient temperature (c) 200lfm 400lfm ambient temperature (c) 20 40 60 80 100 120 0 20 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 maximum load current (a) 4651 f30 40 60 80
28 for more information www.linear.com/ltm4651 applications information figure 31. recommend pcb layout, package top view typical applications figure 32. 1.25a, C24v output dc/dc module regulator gnd gnd v in v d v out ? 4650 f31 *d1 optional (see effect in figure 33): central semiconductor p/n cmmsh1-40l iseta isetb v in sv in v d run clkin intv cc vinreg compa compb pgood gnd sns gnd pgnd v out ? sv out ? pgdfb extv cc temp + temp ? ltm4651 ?24v out up to 1.25a c out 10f 2 load r fset 165k r iset 481k c d 4.7 f v in 12v 4651 f32 f set c dgnd 4.7 f c inout 4.7 f c in 4.7 f 3.3v r pgdfb 100k r pgdfb 196k d1* r extvcc 100 c extvcc 1f lt m4651 4651f
29 for more information www.linear.com/ltm4651 typical applications figure 33. start-up waveforms at 12v in , figure 32 circuit (a) start-up performance with d1 not installed. v out ? reverse-polarity at start-up transiently reaches 500mv 1ms/div v out ? 10v/div v out ? 200mv/div run, 5v/div pgood, 5v/div (b) start-up performance with d1 installed. v out ? reverse-polarity at start-up is transiently limited to 360mv 1ms/div v out ? 10v/div v out ? 200mv/div run, 5v/div pgood, 5v/div lt m4651 4651f 4651 f33a 4651 f33b
30 for more information www.linear.com/ltm4651 figure 34. C24v output at up to 4a from 24v input, 2-phase interleaved, parallel application at f sw = 1.5mhz typical applications iseta isetb v in sv in v d run clkin intv cc vinreg compa compb pgood gnd sns gnd pgnd v out ? sv out ? pgdfb extv cc temp + temp ? u2 ltm4651 r fset2 90.9k r iset2 240k c d2 4.7 f f set c dgnd2 4.7 f c inout2 4.7 f c in2 4.7 f 4651 f34 iseta isetb v in sv in v d run clkin intv cc vinreg compa compb pgood gnd sns gnd pgnd v out ? sv out ? pgdfb extv cc temp + temp ? u1 ltm4651 ?24v out up to 4a load r fset1 90.9k c d1 4.7 f f set c dgnd1 4.7 f c inout1 4.7 f c in1 4.7 f 3.3v r pgdfb 100k r pgdfb1 196k r extvcc1 100 c extvcc1 1f c out 10f 4 v in 24v out1 out2 mod v + set gnd ltc6908-1 r set 66.5k 3.3v r extvcc2 100 c extvcc2 1f r pgdfb2 196k lt m4651 4651f
31 for more information www.linear.com/ltm4651 10ms/div v out + 5v/div v out ? 5v/div run, 5v/div pgood, 5v/div figure 35. current sharing performance of ltm4651s in figure 34 circuit figure 36. concurrent 12v supply, output voltage start-up waveforms. figure 37 circuit typical applications lt m4651 4651f 2.0 2.5 3.0 3.5 4.0 0 0.25 0.50 0.75 1.00 4651 f36 1.25 1.50 1.75 2.00 2.25 module output current (a) 4651 f35 u1 output current u2 output current load current (a) 0 0.5 1.0 1.5
32 for more information www.linear.com/ltm4651 package description table 9. ltm4651 component bga pinout pin id function pin id function pin id function pin id function pin id function pin id function a1 v in b1 clkin c1 nc d1 pgood e1 compb f1 isetb a2 v in b2 nc c2 v out C d2 pgdfb e2 compa f2 iseta a3 v in b3 v in c3 sv in d3 vinreg e3 f set f3 extv cc a4 v d b4 v d c4 v d d4 gnd e4 sv out C f4 run a5 v out C b5 v out C c5 v out C d5 v out C e5 v out C f5 v out C a6 nc b6 nc c6 nc d6 nc e6 nc f6 nc a7 nc b7 nc c7 nc d7 nc e7 nc f7 nc pin id function pin id function pin id function pin id function pin id function g1 gnd sns h1 gnd sns j1 temp + k1 pgnd l1 pgnd g2 sv out C h2 sv out C j2 temp C k2 pgnd l2 pgnd g3 intv cc h3 v out C j3 v out C k3 pgnd l3 pgnd g4 v out C h4 sw j4 v out C k4 v out C l4 v out C g5 v out C h5 v out C j5 v out C k5 v out C l5 v out C g6 nc h6 nc j6 temp + k6 nc l6 nc g7 nc h7 nc j7 temp C k7 nc l7 nc package photograph lt m4651 4651f
33 for more information www.linear.com/ltm4651 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description package top view 4 pin ?a1? corner y x aaa z aaa z bga package 77-lead (15.00mm 9.00mm 5.01mm) (reference ltc dwg# 05-08-1826 rev ?) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (77 places) a detail b package side view m x yzddd m zeee a2 d e bga 77 0417 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module detail a package bottom view 3 see notes a b c d e f g h j k l pin 1 e b f g 7 6 5 4 3 2 1 suggested pcb layout top view 0.000 2.540 3.810 5.080 6.350 1.270 3.810 2.540 1.270 5.080 6.350 3.810 2.540 1.270 3.810 2.540 1.270 0.3175 0.3175 0.000 0.630 0.025 ? 77x 6 see notes 5. primary datum -z- is seating plane 6 package row and column labeling may vary among module products. review each package layout carefully ! symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 4.81 0.50 4.31 0.60 0.60 0.36 3.95 nom 5.01 0.60 4.41 0.75 0.63 15.00 9.00 1.27 12.70 7.62 0.41 4.00 max 5.21 0.70 4.51 0.90 0.66 0.46 4.05 0.15 0.10 0.20 0.30 0.15 total number of balls: 77 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht z detail b substrate a1 ccc z z // bbb z h2 h1 b1 mold cap please refer to http://www.linear.com/product/ltm4651#packaging for the most recent package drawings. lt m4651 4651f
34 for more information www.linear.com/ltm4651 ? ? linear technology corporation 2017 lt 0817 ? printed in usa www.linear.com/ltm4651 related parts typical application figure 37. concurrent 12v supply. see figure 36 for output voltage start-up waveforms pgood run comp intv cc drv cc f set track/ss fcb marg0 marg1 mpgm v out v fb pull-up supply 5v r3 51k c4 0.1f c5 22pf c out1 47f 4 c in1 10f 50v v in 22v to 36v LTM4613 sgnd pgnd margin control r4 51k r fb 5.23k r1 392k 5% margin v d v in pllin c1 to c3 10f 50v 3 v out + 12v up to 8a 4651 f37 iseta isetb v in sv in v d run clkin intv cc vinreg compa compb pgood gnd sns gnd pgnd v out ? sv out ? pgdfb extv cc temp + temp ? ltm4651 v out ? ?12 up to 3.15a c out2 22f load r fset 124k r iset 240k||10k c d 4.7 f f set c dgnd 4.7 f c inout 4.7 f c in2 4.7 f r pgdfb 95.3k r extvcc 49.9 r track 10k c extvcc 1f part number description comments ltm8045 sepic or inverting module dc/dc converter 2.8v v in 18v, 2.5v v out 15v. i out(dc) 700ma. 6.25mm 11.25mm 4.92mm bga ltm8049 dual, sepic and/or inverting module dc/dc converter 2.6v v in 20v, 2.5v v out 24v. i out(dc) 1a/channel. 9mm 15mm 2.42mm bga ltm8073 60v, 3a step-down module regulator 3.4v v in 60v, 0.8v v out 15v. 6.25mm 9mm 3.32mm bga ltm8064 58v, 6a cvcc step-down module regulator 6v v in 58v, 1.2v v out 36v. 11.9mm x 16mm 4.92mm bga LTM4613 en55022b compliant, 36v, 8a module regulator 5v v in 36v, 3.3v v out 15v. 15mm 15mm 4.32mm lga, and 15mm 15mm 4.92mm bga lt m4651 4651f

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